Maximo H. Salinas, Senior Scientist

Center For Semicustom Integrated Systems

CSIS Staff: Maximo H. Salinas

Position: Senior Scientist
Department: Electrical Engineering
Office: Thornton Hall Room
Phone: 804-924-6101	Fax: 804-924-8818
Email: msalinas@virginia.edu

Other Home Pages: EE Dept. Home Page for Maximo H. Salinas

Biography

Max Salinas received a BS in Electrical Engineering from MIT in 1984. After that, he worked for 3 1/2 years as a digital design engineer for a couple of small early computer workstation companies. Next, he came to the University of Virginia and received an MS in Electrical Engineering in 1990. While working towards his Ph.D. in EE here at UVA, an opportunity came along to work full time for the department. First, Mr. Salinas became the senior computer systems administrator, and later a Research Scientist in the department's Center for Semicustom Integrated Systems (CSIS). His current position is Senior Scientist. In his very limited spare time, Max still continues work on his Ph.D.

Current Research

SMC

The Stream Memory Controller project involves faculty, staff, and students from the EE and Computer Science departments. The project involves the specification and implementation of a novel intelligent memory controller which can be used in vector memory operations to reorder the memory access patterns so that the effective bandwidth between the CPU and memory can be greatly increased. Note that the SMC is not a cache! Caches are not particularly good for accesses that will only touch each item of memory once. An SMC complements a cache in a system by increasing the effective bandwidth for operations in which a cache is not very helpful. Using tools from Mentor Graphics Corporation, Summit Design Systems, and Cascade Design Automation, a 71,000 transistor IC was designed and subsequently fabricated using the MOSIS VLSI Fabrication Service at the University of California's Information Sciences Institute.

Isotach

The Isotach project involves faculty, staff, and students from the EE and Computer Science departments. The project involves the development of a novel network employing a logical time mechanism that enables message transmitters and receivers to guarantee certain properties about how network messages are serviced. For example, atomicity and sequential consistency can be enforced easily. Project sponsors include NSF, ARPA, NGIC, and Mystech Associates.

RASSP Education and Facilitation

RASSP is a program funded by ARPA and the Tri-Services with the goal of providing a 4x improvement in many areas of signal processing systems. The RASSP Education and Facilitation project (RASSP E&F), headed by the South Carolina Reseach Authority (SCRA), performs three primary functions in the RASSP program. First, the E&F team develops educational material so that advances from the program can be communicated to universities and to the system design community at large. Second, it assists individual companies interested in incorporating RASSP principles into their design flows. Third, it maintains a RASSP E&F web page to provide current information on upcoming events, RASSP-related instructional material, documents, and lots more.

Computer Architecture Level Modeling (CALM)

On my Ph.D. research, I am developing a methodology and specifying a suite of tools that will allow a designer or system modeler to create a functional description of a computer's instruction-set-architecture very rapidly. The work is loosely based on the Implementation-Independent Modeling methodolgy developed as part of my M.S. work. Summaries of the I-I methodology are readily available either here or in the September 1993 issue of the IEEE Design & Test of Computers.

Publications

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