Text-Only CSIS Pages
Research at the Center for Semicustom Integrated Systems
The Stream Memory Controller project involves faculty, staff, and
students from the EE and
Computer Science departments. The project involves the
specification and implementation of a novel intelligent memory
controller which can be used in vector memory operations to reorder the
memory access patterns so that the effective bandwidth between the CPU
and memory can be greatly increased.
Note that the SMC is not a cache!
Caches are not particularly good for accesses that will only touch
each item of memory once. An SMC complements a cache in a system by
increasing the effective bandwidth for operations in which a cache is
not very helpful.
Using tools from Mentor Graphics
Corporation, Summit Design Systems,
and Cascade Design Automation, a
135,000 transistor IC was designed and
subsequently fabricated using the MOSIS VLSI Fabrication
Service at the University of California's Information Sciences
Institute.
The Isotach project involves faculty, staff, and
students from the EE and
Computer Science departments. The project involves the
development of a novel network employing a logical time mechanism that
enables message transmitters and receivers to guarantee certain
properties about how network messages are serviced. For example,
atomicity and sequential consistency can be enforced easily.
Project sponsors include NSF,
ARPA, NGIC,
and Mystech Associates.
Quest
Quest is an acronym for "Quick Execution of Simulation, Synthesis and Test."
The CSIS is conducting research into parallel algorithms for test
generation for large scale digital systems. This research is being
conducted as part of the Quest project in cooperation with the
Electrical and Computer Engineering
Department at the University of
Cinncinatti.
The RASSP (Rapid-Prototyping of Application Specific Signal Processors) program
is a broad research initiative to reinvent electronic design. The goal is to
dramatically improve the design cycle, dependability, and cost of complex
digital signal processing systems. Although the scope is realistically
focused on DSP systems, the RASSP methodology, infrastructure, and architecture
is applicable to other system designs. For more information, visit the
RASSP site.
RASSP is a program funded by ARPA and the Tri-Services with the
goal of providing a 4x improvement in many areas of signal processing
systems. The RASSP Education and Facilitation project (RASSP E&F),
headed by the South Carolina Reseach Authority
(SCRA), performs three primary functions in the RASSP program.
First, the E&F team develops educational material so that advances
from the program can be communicated to universities and to the
system design community at
large. Second, it assists individual companies interested in
incorporating RASSP principles into their design flows. Third, it
maintains a RASSP E&F web
page to provide current information on upcoming
events, RASSP-related instructional material, documents, and lots more.
Gastric Pacemaker
The CSIS's
Systems Integration Laboratory is developing a gastric pacemaker, in
cooperation with the U.Va. Department of
Internal Medicine. This is a patented technology
that uses electrical pulses to stimulate the digestive process in patients with
paralyzed stomachs.
Quartz Pressure Transducer
A miniaturized, quartz pressure transducer system has been developed for Pressure Systems Inc. of Hampton,
Virginia. It will be used primarily to measure pressure on the control surfaces of aircraft scale models
during wind tunnel testing. This two-board system is only 1.2 inches in diameter
and contains a complete on-board computer as well as signal processing.
Optical Micrometer
An optical micrometer, developed for Virginia Semiconductor
Incorporated, permits for the nondestructive absolute
thickness and total thickness variation measurement of
silicon wafers. This system was originally designed for use with a dedicated
68HC11 processor which measured the absolute thickness of wafers. A second
version of the project was completed in June 1997 which incorporated a PC
interface running LabView software which CSIS engineers designed to control
stepper motors for stage control, automatic data logging of wafer thickness
as well as Total Thickness Variation images which provide a "topographical" map
of the wafer smoothness. These images are developed using an infared laser and camera
and brought into the PC and stored as bitmaps using LabView's IMAQ Vision system.
DIFtree
DIFtree (Dynamic Innovative Fault Tree) is both a methodology
and prototype software tool providing a unique approach for
reliability analysis of complex computer-based systems.
DIFtree combines the best of static and dynamic fault
tree analysis techniques using a modular analytical
approach, and unique in several aspects:
First, the detection of modules in a fault tree uses a fast and
efficient algorithm to identify independent pieces. These
independent submodels can be solved separately, thereby
allowing an exact solution in minimum time.
Second, the submodels are classified as either static
or dynamic, depending on the temporal relationships between
the input events. Static subtree gates express the failure criteria
in terms of combinations of events. Dynamic
subtree gates express the failure criteria in terms
of combinations and order of occurrence for input events.
More important than the classification, however, is that
the different subtree types are solved using different
solution techniques. That is, the static subtrees are
solved using combinatorial methods (specifically a method
based on Binary Decision Diagrams) while the dynamic subtrees
are solved using Markov methods.
Third, since it is known that modeling the possibility of
imperfect fault coverage is critical
to correct evaluation of computer-based systems, we include
this capability in both the static and dynamic solution techniques.
Fourth, the solution of static fault trees using methods
based on Binary Decision Diagrams, and including imperfect
coverage in this solution, is unique to our approach. The
BDD approach to fault tree analysis is a new innovation which
holds great potential for the analysis of large models.
Fifth, the dynamic fault tree model allows the analysis of
complex redundancy management techniques in a relatively
simple manner.
Factors which normally lead to difficulties with analysis, include
cold, warm and hot spares, spares which are shared
among several different components, functional dependencies and
common-cause failures; these and more are handled easily
using our special dynamic gates.
Sixth, our modular approach to dynamic models can allow the
analysis of much larger systems than with traditional (non-modular)
approaches. Further, the identification of independent submodels
is significantly easier in our approach, since it is done at
the fault tree level. It is not feasible, in
general, to detect modules directly in a Markov model.
Seventh, our methodology provides an exact solution in several
cases where most other methods provide an approximation, at
best. These cases include those where events are repeated
(a very common occurrence in fault tolerant systems),
large systems, systems in which probabilities and rates of failure
are arbitrarily combined, as well as other more subtle situations.
Further, since our methodology allows the combination of
constant probabilities and rates of occurrence, it is
therefore applicable to more than just hardware. Our
methodology is equally applicable to software and human
operator failures as well as hardware failures, and
thus is well suited to the analysis of complex
computer based systems.
Union Switch and Signal
The Union Switch & Signal (USS) project is a joint research effort between
the University of Virginia and USS, Inc. of Pittsburgh, PA. The objective is
to develop a next-generation embedded control system for the railway
industry. This project offers several unique opportunities for students,
faculty, and staff.
Significant contributions from the project to date are:
- development of a fault simulation methodology for the validation
and verification (V & V) of safety-critical systems. Using this
methodology, a V & V was performed on an existing USS system as a
proof of the developed concepts.
- development of a fault list generation algorithm to enumerate
transient data faults which if undetected cause a system failure.
Fault simulation of the enumerated faults is then performed to
evaluate fault tolerant aspects of the system under test.
- produced a Variance Reduction Technique (VRT) to increase the
accuracy of fault coverage estimates. Typically, fault coverage
estimation is performed by analyzing fault simulation data. The
developed VRT relies on exploiting fault equivalency in the system
under test. Equivalent fault sets are determined by a process
referred to as fault expansion. Two faults are defined to be
equivalent so long as the system response to both faults is
identical. The VRT technique was applied to an existing USS
system to estimate fault detection coverage.
Rome Laboratory
The Rome Lab project involves the development of a fault simulation tool
that will allow a designer to perform fault simulation on a VHDL model in an
automated fashion. One unique aspect of the fault simulator is that it is
independent of any EDA design tool although it can easily be incorporated
with any tool. Another unique aspect is that the fault injection mechanism
is implemented entirely in VHDL and based on an IEEE standard. So, it can
be used with any 1076-compliant VHDL simulator. Significant contributions
to date are:
- development of a VHDL-based fault injection mechanism that can be
used to perform fault simulation using any VHDL-compliant
simulator. The fault injection mechanism is based on IEEE
standard 1029.1-1996 (WAVES-96). Also developed VHDL
implementations of the four of the more popular fault models to
use for fault simulation: (1) stuck-at fault model, (2) bridging
fault model, (3) stuck-open fault model, and (4) delay fault model.
- Formation of a fault simulation working group under the Design
Automation Technical Committee (DATC) to study the problem of
fault simulation using VHDL and/or Verilog. The expected outcome
from this working group is an IEEE standard for fault simulation
using VHDL and/or Verilog.
- Development of a methodology to provide unbiased estimates of
dependability metrics and parameters of a highly-dependable system
by testing an appropriate subset of the entire fault set. This
methodology will use statistics of the extremes to analyze rare
event data, such as the occurence of a fault in an ultra-reliable
system. In particular, coverage modeling will be examined and the
developed methodology will be extended to modeling other
hardware/software dependability metrics and parameters.
- Fault simulation has been effective in monitoring the response of a
system to anomalous events from both external sources and internal
states. The work performed under this project sought to address
three shortcomings in state-of-the-art fault simulation: (1) fault
simulation is performed in models of systems that are distinct
from synthesizeable designs, (2) fault simulation is supported at
only a single level of design abstraction, and (3) fault
simulation is performed for either hardware descriptions of
components or software programs -- a partial solution to system
design and analysis. The work performed under this project has
supported fault simulation in VHDL design models of hardware
systems that can be and have been subsequently synthesized in
hardware. The method by which faults are injected is through
non-intrusive signal corruption. This approach does not require
modification of hardware descriptions for fault simulation. The
fault simulation methodology can be applied throughout the design
process of systems from architectural level models, to
register-transfer models, to gate-level descriptions. Finally,
fault simulation in VHDL has been integrated with fault simulation
in C to support hardware/software co-design and analysis. A
supporting set of fault simulation utilities have been built onto
the Mentor Graphics design environment to support seamless design
and analysis.
These pages are designed to give you an
idea of what we are doing here at the University of Virginia. The
research projects are a part of the overall effort of the Applied
Electrophysics Laboratory (AEpL) and Center for Semicustom Integrated
Systems (CSIS). Research is generally related to electronic materials
and materials processing, semiconductor device design and fabrication,
and semiconductor integrated circuits. More specifically, research
topics include millimeter wave Transferred Electron Oscillators,
millimeter wave frequency multipliers, numerical device simulation,
nonlinear high frequency circuit analysis, processing and analysis of
ultra thin silicon substrates, and integrated analog/digital silicon
microinstruments. Teaching activities range across all levels of the
Electrical Engineering curriculum and are generally related to
engineering design.
nView Corporation (Newport News, VA)
Interaction with a Computer Generated Image
The overall objective of the project is to develop an interactive "blackboard"
where images on the "blackboard" are projected from a computer screen, and one
or more users can interact with the images using "electronic markers."
nView Corporation is a Virginia manufacturer of overhead projectors of computer
images. These projectors are based on liquid crystal displays. nView currently
has a patent pending on the technology necessary to interact with these images.
CSIS is participating in developing an implementation of this technology. The
CSIS involvement has principally been in the area of development of a sensor to
read the position of the electronic marker on the projected image. A prototype
of this device is shown in the photograph above.
The development of this prototype has required the design of sophisticated analog
sensors and amplifier technology. The prototype circuit board was developed using
state-of-the-art board level CAD tools and the in-house CSIS surface mount
capability.
Last modified: June 5, 1998
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