On this page is a list of all papers written by CSIS faculty and staff that are currently offered in the online library. These are all in postscript format, and selecting the paper title will download the paper. Papers are organized alphabetically by first author listed.

Alexander M. J., J. P. Cohoon, J. L. Ganley, and G. Robins, An Architecture-Independent Approach to FPGA Routing Based on Multi-Weighted Graphs, European Design Automation Conference, Grenoble, France, September, 1994.

DeLong, Todd A., Barry W. Johnson, and Joseph A. Profeta, III, "A Fault Injection Technique for VHDL Behavioral-Level Models", to be published in Design & Test.

DeLong, Todd A., Barry W. Johnson, Danielle Bozzolo, and Joseph A. Profeta, III, "A Novel Fault Injection Technique for Behavioral Level Modeling using VHDL", VHDL International Users' Forum Fall Conference, November 13-16, 1994.

DeLong, Todd A., Anup K. Ghosh, and Barry W. Johnson, "Fault Injection in the Design Process using VHDL", VHDL International Users' Forum Fall Conference, October 15-19, 1995.

DeLong, Todd A., Anup K. Ghosh, and Barry W. Johnson, "Fault Injection for Logic Synthesis Design using VHDL", Mentor Users Group Conference, October 22-26, 1995.

Dungan, William W., Robert H. Klenke, James H. Aylor, "Mixed-Level Modeling in VHDL Using the Watch-and-React Interface", Proceedings of the Fall VHDL International Users Forum, 1997, pp25-32.

Garrett, David and Mircea Stan, "Power Reduction Techniques for a Spread Spectrum Correlator", Proceedings of the International Symposium on Low Power Electronics and Design Conference, 1997.

Garrett, David and Mircea Stan, "Low-Power Design Environment for MOSIS", Proceedings of the Mentor Graphics Users' Group Conference, 1997.

Ganley, J.L., and J. P. Cohoon, Optimal Rectilinear Steiner Minimal Trees in O(n^2 2.62^n) Time, Sixth Canadian Conference on Computation Geometry, Saskatchewan, Canada, August 1994.

Ganley, J.L., and J. P. Cohoon, Routing a Multi-terminal Critical Net: Steiner Tree Construction in the presence of Obstacles IEEE International Conference on Circuits and Systems, London, UK, pp. 113-116, June 1994.

Ganley, J.L. and J. P. Cohoon, A Faster Dynamic Programming Algorithm for Exact Rectilinear Steiner Minimal Trees, ACM/IEEE Great Lakes Symposium, South Bend, IN, pp. 238-241, March 1994.

Klenke, Robert H., Andrew P. Voss, James H. Aylor, "Performance Modeling of Multicomputer Systems in VHDL using ADEPT", Proceedings of the IASTED International Conference on Modeling and Simulation, 1997, pp 429-438.

McGraw, Robert, James H. Aylor, Robert H. Klenke, "A Top-down Design Environment for Developing Pipelined Datapaths", To Appear in the Proceedings of the Design Automation Conference 1998.

Prey, J.C., J. P. Cohoon, and G. Fife, Software Engineering Beginning in the First Computer Science Course, SEI Conference on Software Engineering Education, San Antonio, TX, December 1993.

Smith, D. Todd, B. W. Johnson, and J. Profeta, "System Dependability Evaluation Via a Malicious Fault List Generation Algorithm" , IEEE Transactions on Computers, (accepted for publication).

Smith, D. Todd, B. W. Johnson, N. Andrianos, and J. Profeta, "A Variance Reduction Technique via Fault Expansion for Fault Coverage Estimation", IEEE Transactions on Reliability, (submitted for publication).

Smith, D. Todd, B. W. Johnson, J. Profeta, and D. Bozzolo, "A Fault List Generation Algorithm for the Evaluation of System Coverage", Reliability and Maintainability Symposium,1995, pp. 425-432.

Smith, D. Todd, B. W. Johnson, J. Profeta, and D. Bozzolo, "A Method to Determine Equivalent Fault Classes for Permanent and Transient Faults", Reliability and Maintainability Symposium,1995, pp. 418-424.

Stan, Mircea, David Garrett, Abhimanyu Kolla, and Zaid Salman, "Schematic Driven Layout Using the MOSIS Design Kit for Advanced Analog and Mixed-Signal Design", Proceedings of hte Mentor Graphics Users' Group Conference, 1997.

Voss, Andrew P., Robert H. Klenke, James H. Aylor, "The Analysis of Modeling Styles for System Level VHDL Simulations", Proceedings of the Fall VHDL International Users Forum, 1995, pp1.7-1.13.

Last Modified: Apr. 28, 1998

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